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Verification 3.0 Innovation Summit

Verification 3.0 Innovation Summit


15 of the Industry’s leading verification technology companies hosted the inaugural Verification 3.0 Innovation Summit on March 19, 2019 at Levi’s Stadium in Santa Clara with Joe Costello, former CEO of Cadence, delivering the keynote.

During this event, Methodics presented a paper titled “Traceability of the Design Verification Process.” To download and read the complete paper, please log into our Resource page at

For a summary of the entire event and to see the presentations, please visit

DVCON-U.S. 2019

DVCON-U.S. 2019


February 25 - 28, 2019

DoubleTree Hotel, San Jose, CA
Booth 605


The ability to correlate verification results back to specific hierarchical design versions and, ultimately, to the original design requirements for each design is mission-critical for semiconductor companies who must meet and prove compliance with important Functional Safety (FuSa) standards such as ISO26262.

Methodics 2018 User Group Summary

Methodics 2018 User Group Summary

Many thanks to the customers who attended the annual Methodics User Group Meeting 
in June, 2018 and helped make it a huge success!

Also, we’d like to extend a very special Thank You to Maxim Integrated 
for allowing us to hold the event at their wonderful facility in San Jose!

At the event, our customers were able to network with fellow IC designers and IP management experts, find out how others are using Methodics solutions, share ideas, methodologies, and best practices, and review and provide valuable feedback to us regarding our product roadmap.

The many topics covered during the two day event included:

  • Analog IP reuse

  • Corporate IP Cataloging with Percipient

  • Continuous Integration Flows for IP-centric design

  • IP-centric SOC assembly

  • Managing Variants in an IP-centric environment

  • 3rd Party IP Acceptance Testing & Quality Management

  • Having a common platform for both 3rd party and internal IP development and validation

  • Design Traceability for ISO26262 and other requirements

For reference, here is the agenda we covered during the two day event:

Agenda - Day 1

9:00 - Coffee, Meet and Greet
9:30 - Industry Vision Presentation
         "Semiconductor Landscape 2020"
          Simon Bennett
          Director, R&D Strategy Enabling, Intel
10:00 - Customer Presentations

  • "Working Towards Trunk-Based IP Management"
    Maxim Integrated

  • "Enabling Global Design Infrastructure",
    Analog Devices Inc.

  • "IP Versions, Hierarchy, Workspaces, Security, and Development Workflows"
    Silicon Labs

12:00 - Lunch provided by Methodics
1:00 - Customer Panel Discussion
1:30 - Round Table Discussions on Common
4:00 - Round Table Summaries
5:00 - Daily Wrap-Up
5:30 - Private Happy Hour on the patio at the Faultline Brewing Company in Sunnyvale, sponsored by our PLM Partner, Siemens!

Agenda - Day 2

9:00 - Coffee, Meet and Greet
9:30 - Methodics R&D Discussion based on Day 1
           Customer Input
11:00 - Methodics R&D Roadmap Presentation and
12:00 - Lunch provided by Methodics
1:00 - Break-Out Sessions
5:00 - Meeting Wrap-Up and Adjourn

For more details on the event, the presentations, or on the upcoming 2019 Methodics User Group meeting, please contact us.

CDNLive EMEA 2018

CDNLive EMEA 2018

Monday, May 7, 2018 – Wednesday May 9, 2018


May 7- 9, 2018
INFINITY Hotel & Conference Resort Munich—Unterschleissheim, Germany

More Information




June 8 from 10 - 11AM PDT

New Concepts in Semiconductor IP Lifecycle Management

Today's complex SoC design requires a new level of internal and external design traceability and reuse by tightly coupling IP creators with IP consumers. Join us for the introduction of an exciting new platform that allows companies to provide the transparency and control needed to streamline collaboration by providing centralized cataloging, automated notifications to design teams, flexible permissions across projects, and integrated analytics across diverse engineering systems. Come see how companies are realizing substantial cost and time to market savings by adopting IP lifecycle management methodologies.

To view the video of the webinar, please CLICK HERE.

CDNLive - Silicon Valley - 2017

CDNLive - Silicon Valley - 2017

CDNLive - Silicon Valley

April 11th, 2017 - Exhibit and Presentation

"Meeting Time-to-Market and Cost Reduction Goals through Platform Based Design"
1:30 pm
in the Tensilica & Design IP track