Fascinated by computers at a very young age, Peter got his degree in Computer Science and was brought to the Bay Area via AIESEC Berkeley’s student exchange program to write his thesis. He has now more than 15 years of professional experience in software engineering, large scale systems architecture and data center engineering in Silicon Valley startups as well as with Yahoo! where he spent the last 9 years as a systems architect and principal engineer.
Small EDA companies often focus on a single point tool and then gradually over time they add new, complementary tools to start creating more of a sub-flow to help you get that next SoC project out on time. The most astute EDA companies often choose to partner with other like-minded companies to create tools that work together well, so that your CAD department doesn't have to cobble together a working solution. I was pleased to find two such EDA companies that have worked well together on SoC integration using IP lifecycle management methodology, Methodics and Magillem.
In this customer environment 200GB workspaces are common and can take up to 30 mins to fully populate. The general logistics around disk space management, delays in getting up current design data and NFS latencies were a major source of delay for designers with a material impact on time-to-market.
Multiple workspaces created for regression runs can overwhelm traditional lers when they write back regression results and log les. This is particularly true when many short tests complete at roughly the same time. With WarpStor’s buffered write-through cache accumulating writes and bursting them to the ler, write performance can be dramatically increased.
As semiconductor companies adopt IP reuse strategies to improve engineering efficiencies and achieve time-to-market advantages, modern data management (DM) tools are built on industry standard version control systems that provide a "single-source-of-truth" architecture.
In his latest article "IC Design Management: Build or Buy?" on SemiWiki, Daniel Payne discusses the benefits of this architecture in contrast to commercial or homegrown systems built around an older style "server-per-project" architecture.
You can read the complete article here: https://www.semiwiki.com/forum/content/6388-ic-design-management-build-buy.html
Leveraging ‘Single Source of Truth’ Architecture to Speed Development Times, Improve Design Quality, and Reduce Risk
Many Design Management (DM) tools used by the Semiconductor Industry today are based on outdated, proprietary version control systems and have fallen significantly behind the state of the art. These tools are often only capable of supporting a single project per server due to the severe scalability and performance limitations inherent in their underlying technology. This ‘server per project’ limitation siloes teams and their information, preventing sharing and reuse across the organization.
This paper describes how modern DM tools are built on industry standard version control systems to take a centralized, IP based approach - one that leverages a ‘Single Source of Truth’ architecture for Platform Based Design and enables a high degree of design reuse to speed development times, improve quality, and reduce risk.
"IP" and "IP Reuse" mean different things to different people. For many years, Methodics has been helping semiconductor companies implement IP reuse strategies. In this interview, Simon covers important trends in methodologies that help customers stay competitive in the face of ever-tightening margins.
This paper describes how a requirements management system like Jama can be integrated into the IP management platform ProjectIC, allowing users to see IP requirements right in the context of their SoC.
Such integration represents one more step forward to reaching the important goal of implementing IP reuse strategies that reduce development costs, improve time-to-market, and keep semiconductor companies profitable in today’s highly competitive SOC marketplace.
Semiconductor design IP and verification IP have been around for decades, but just because your company has lots of IP doesn't mean that you're getting all of the benefits of a design reuse methodology. Here are 5 reasons why platform based design can help your next SoC.
Companies designing today's complex System-on-Chips (SoC’s) must find new ways to meet the challenges imposed by shrinking time-to-market windows and cost pressures. Platform based design methodologies allow companies to reduce the time it takes to bring designs to market and maximize reuse of internal IP on those designs. A platform is the starting point for a new or derivative design that contains all of the IP and design meta data properly configured to be downloaded to a user's workspace. To enable a platform based design methodology, companies must formalize how design IP is handled. By adopting an IP Lifecycle Management solution (IPLM), companies can benefit from streamlining the SoC development process and guarantee that IP is being fully utilized through all of the company’s design projects.
In this customer environment, 200GB workspaces are common and can take up to 30 mins to fully populate. The general logistics around disk space management, delays in getting up current design data, and NFS latencies were a major source of delay for designers with a material impact on time-to-market.
The team installed a WarpStor appliance including local storage on their network and project workspaces were built on the appliance. User workspace creation time and disk space needs were reduced dramatically:
- Average workspace population time was reduced from 20-30mins to 14s
- User workspace sizes decreased from 150GBto 100KB
- Total IOPs down by more than 70% during write bursts
Multiple workspaces created for regression runs can overwhelm traditional lers when they write back regression results and log files.
The team installed a WarpStor appliance in front of their SAN. All regression workspaces were built on the WarpStor appliance. Filer write performance was improved dramatically:
- Up to 10x reduction in random writes due to buffering/coalescing on WarpStor Appliance
- Up to 20% improvement in raw throughput of random writes
- Utilization of the filer reduced by almost 50% during write bursts
- Total IOPs down by more than 70% during write bursts
DAC 2016 in Austin will be another exciting event for Methodics. We'll be featuring the second major release of our IP Lifecycle Management platform, ProjectIC, along with a new release of WarpStor, our partnerships with Perforce and Magillem, hula dancers, and much more!
Welcome to Our DAC 2016 Newsletter!
Come see us at DAC 2016 in Austin
White Paper: Meeting Time-to-Market
and Cost Reduction Goals Through Platform Based Design
by: Michael Munsey, VP of Business
Development and Strategic Accounts
Time-to-Market and Cost Reduction Goals Through Platform
Consumer demands will continue to pressure companies to deliver new and innovative products. SoC design companies need to find ways to meet ever shrinking market windows while design complexity continues to grow.
Platform based design methodologies allow SoC design teams to deliver against these technology and market pressures by allowing for maximum design reuse and simplification of the new product design development environment. The key to enabling this methodology is the ability to organize all the company's design assets into a base set of design platforms and to institute an IP Lifecycle Management system to support this methodology.
Most design teams - be it semiconductor designers, artists, video producers, game developers - are struggling with an unprecedented deluge of data. Design workspaces have grown, often into multiple Gigabytes, sometimes into 100’s of Gigabytes.
Because of this, the version control tool is constantly under pressure to serve large amounts of data to individual workspaces. These workspaces consume terabytes of data on the filers, and the networks are clogged by NFS moving data between filers and mounting the resulting workspaces onto clients. And additional workflows, such as Continuous Integration (CI), make the situation even worse.
However, there is a clear structure inherently associated with each user's workspace. This structure can be analyzed and leveraged to build very compelling solutions to reduce the load on the version control tools, putting them on figurative ‘steroids’. This paper presents such a methodology and solution.
Methodics makes a point at appearing with our good Partner Cadence at most of their CDN Live events. We'll be continuing this tradition by appearing at the Israel CDN Live event next week. Please email us if you'd like to setup a demo of any of the Methodics IP Management solutions - email@example.com
Should a semiconductor/IP company use a proprietary data-management (DM) environment? Or even develop their own? After all, every company is unique and developing a unique DM allows a perfect match of just what is required for that particular company. And, in principle, a proprietary DM system can underpin the design management solution perfectly. Or maybe not...
For the top 10 reasons to use industry standard data management, read Paul McLellan's SemiWiki blog here.
Methodics was proud to have participated as a speaker and a sponsor at the Perforce 2016 MERGE conference, held recently in San Francisco from April 13 to 15, 2016.
During the conference, we presented ways that mutual customers can dramatically reduce the load on their network, storage filers, and Perforce servers while also making very large, near-instant workspaces available to users.
As a result of our participation, we had lots of great discussions directly with customers. These opportunities are always valuable to keeping our product roadmaps on track.
During the conference we were awarded the 2016 "Versionary" award for "Most Innovative Integration". Thanks for the recognition Perforce! and thanks to all our customers that made this possible.
Pictured left-to-right are Simon Butler (Methodics Founder and CEO), Jerry Brocklehurst (Methodics VP of Worldwide Sales & Marketing), and Chris Dobbrow (Perforce VP of Strategy and Key Accounts)
SoC Integration is a challenging and important task that all hardware teams undertake on a regular basis.
A SoC is typically made up of series of IPs, each of which could also be a sub-system in its own right. The key role of integration is to accept new releases of the component IPs and/or sub-systems, and verify whether these newer releases work in the context of the SoC. The releases that are available for integration should have passed some quality control of their own - i.e. basic checks that ensure that the release that is available for integration satisfies a minimum quality level, and moves the SoC forward.
This white paper describes an integration flow methodology, and how various roles involved in the process - integrator, contributor, and consumer - interact to assure successful integration of component IPs and sub-systems.