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Improving Time-To-Market With The Right IPLM Solution

Improving Time-To-Market With The Right IPLM Solution

Introduction

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In the increasingly competitive semiconductor market, getting a product out on time is of critical importance. Missing market windows by even a few months can mean the difference between being highly profitable vs breaking even or even losing millions in revenue.

In this scenario, it is of critical importance for teams to be able to reuse existing, proven IPs to reduce development time, complexity and cost. An IPLM (IP Lifecycle Management) solution like Methodics’ Percipient is designed to help customers adopt an IP-centric design flow to address this need.

To fully capitalize on IP reuse, the IPLM system needs to be built from the ground up to handle the realities and complexities of identifying and reusing IP resources . This white paper discusses one of the key components of Percipient - the Graph Database - that helps the tool achieve its goal of enabling fast and seamless IP reuse.

Something New in IP Lifecycle Management

Something New in IP Lifecycle Management

Last month at DAC I met up with Michael Munsey of Methodics to get a quick update on what has been happening over the past 12 months within his company, and he quickly invited me to watch an archived webinar on their latest tool for IP Lifecycle Management called Percipient. I love to play the board game Scrabble, so i had to Google the word Percipient to learn its meaning, "having a good understanding of things, perspective". OK, that's my new word for the day then.

We often blog about new and updated point EDA tools on SemiWiki, so it's refreshing to learn more about the category of EDA tools that works throughout all of the tools and IP used on a SoC project. System-level complexity has become so large that the days of using Excel to track semiconductor IP usage or EDA tool usage fall woefully inadequate. 

CLICK HERE  to read the article

NEW CONCEPTS IN SEMICONDUCTOR IP LIFECYCLE MANAGEMENT

NEW CONCEPTS IN SEMICONDUCTOR IP LIFECYCLE MANAGEMENT

Right before #54DAC I participated in a webinar with Methodics on "New Concepts in Semiconductor IP Lifecycle Management" with Simon Butler, CEO of Methodics, Michael Munsey, Vice President of Business Development and Strategic Accounts, and Vishal Moondhra, Vice President of Applications. The webinar introduced “percipient” and how it will not only extend IP Lifecycle Management, but allow for the modeling of the entire design ecosystem. Percipient was then featured in the Methodics booth at #54DAC with demos and presentations. 

CLICK HERE  to read the article.

THE SEMICONDUCTOR BRIDGE: A CONNECTED IPLM

THE SEMICONDUCTOR BRIDGE: A CONNECTED IPLM

Electronic Design Magazine, June 26, 2017


Development processes in large semiconductor organizations need to scale, and they can do so by adopting the same flexibility and agile principles as software companies.

CLICK HERE to read the article.

Webinar -New Concepts in Semiconductor IP Lifecycle Management

Webinar -New Concepts in Semiconductor IP Lifecycle Management

The semiconductor IP market continues growing at a healthy rate, and IP reuse is a staple of all modern SoC designs. Along with the acceptance of IP reuse comes a host of growing challenges, like:
 

  • Increase in design files
  • Increase in meta-data
  • More links between design members worldwide
  • More links between data in multiple engineering systems


Companies like Methodics have been serving the IP lifecycle management segment for many years now, however there comes a point where the increases in design complexity call for a new approach, so to find out what is coming next you are invited to a webinar where their next generation platform is being unveiled:

CLICK HERE  to read the article.

NEW CONCEPTS IN SEMICONDUCTOR IP LIFECYCLE MANAGEMENT

NEW CONCEPTS IN SEMICONDUCTOR IP LIFECYCLE MANAGEMENT

Excel is a wonderful, general purpose spreadsheet tool that lets me organize and analyze rows and columns of data into something meaningful, however it doesn't know anything about requirements traceability for complex semiconductor projects. So why do so many engineering teams still rely upon Excel or custom, in-house tools? It's probably because of perceived lower costs, institutional momentum, and the typical NIH (Not Invented Here) syndrome. Safety critical industries like automotive, aircraft and medical all have standards that must be adhered to during the design process, and they share a common need - requirements traceability from concept through production. Two software companies have teamed up to integrate their toolsets into something that really does help teams achieve requirements traceability, Jama Software and Methodics. I just attended their joint webinar and will share what they talked about.

CLICK HERE  to read the article.

CTO Interview: Peter Theunis of Methodics

CTO Interview: Peter Theunis of Methodics

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Fascinated by computers at a very young age, Peter got his degree in Computer Science and was brought to the Bay Area via AIESEC Berkeley’s student exchange program to write his thesis. He has now more than 15 years of professional experience in software engineering, large scale systems architecture and data center engineering in Silicon Valley startups as well as with Yahoo! where he spent the last 9 years as a systems architect and principal engineer.

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SoC integration using IP Lifecycle Management Methodology

SoC integration using IP Lifecycle Management Methodology

Small EDA companies often focus on a single point tool and then gradually over time they add new, complementary tools to start creating more of a sub-flow to help you get that next SoC project out on time. The most astute EDA companies often choose to partner with other like-minded companies to create tools that work together well, so that your CAD department doesn't have to cobble together a working solution. I was pleased to find two such EDA companies that have worked well together on SoC integration using IP lifecycle management methodology, Methodics and Magillem

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Fabless SOC Design Company - Creating Large Workspaces with WarpStor

Fabless SOC Design Company - Creating Large Workspaces with WarpStor

In this customer environment 200GB workspaces are common and can take up to 30 mins to fully populate. The general logistics around disk space management, delays in getting up current design data and NFS latencies were a major source of delay for designers with a material impact on time-to-market. 

U.S. Based Flash Memory Company - Improving Filer Random Write Performance with WarpStor

U.S. Based Flash Memory Company - Improving Filer Random Write Performance with WarpStor

Multiple workspaces created for regression runs can overwhelm traditional lers when they write back regression results and log les. This is particularly true when many short tests complete at roughly the same time. With WarpStor’s buffered write-through cache accumulating writes and bursting them to the ler, write performance can be dramatically increased. 

IP Reuse Requires a Single-Source-of-Truth

IP Reuse Requires a Single-Source-of-Truth

As semiconductor companies adopt IP reuse strategies to improve engineering efficiencies and achieve time-to-market advantages, modern data management (DM) tools are built on industry standard version control systems that provide a "single-source-of-truth" architecture.  

In his latest article "IC Design Management: Build or Buy?" on SemiWiki, Daniel Payne discusses the benefits of this architecture in contrast to  commercial or homegrown systems built around an older style "server-per-project" architecture.

You can read the complete article here:  https://www.semiwiki.com/forum/content/6388-ic-design-management-build-buy.html

Leveraging ‘Single Source of Truth’ Architecture to Speed Development Times, Improve Design Quality, and Reduce Risk

Leveraging ‘Single Source of Truth’ Architecture to Speed Development Times, Improve Design Quality, and Reduce Risk

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Many Design Management (DM) tools used by the Semiconductor Industry today are based on outdated, proprietary version control systems and have fallen significantly behind the state of the art. These tools are often only capable of supporting a single project per server due to the severe scalability and performance limitations inherent in their underlying technology. This ‘server per project’ limitation siloes teams and their information, preventing sharing and reuse across the organization.

This paper describes how modern DM tools are built on industry standard version control systems to take a centralized, IP based approach - one that leverages a ‘Single Source of Truth’ architecture for Platform Based Design and enables a high degree of design reuse to speed development times, improve quality, and reduce risk.

All Things IP: SemiWiki's Daniel Nenni interviews Methodics CEO, Simon Butler

All Things IP: SemiWiki's Daniel Nenni interviews Methodics CEO, Simon Butler

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"IP" and "IP Reuse" mean different things to different people.  For many years, Methodics has been helping semiconductor companies implement IP reuse strategies.  In this interview, Simon covers important trends in methodologies that help customers stay competitive in the face of ever-tightening margins.  

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Integrating Requirements Management with IP Management

Integrating Requirements Management with IP Management

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This paper describes how a requirements management system like Jama can be integrated into the IP management platform ProjectIC, allowing users to see IP requirements right in the context of their SoC.

Such integration represents one more step forward to reaching the important goal of implementing IP reuse strategies that reduce development costs, improve time-to-market, and keep semiconductor companies profitable in today’s highly competitive SOC marketplace. 

5 Reasons Why Platform Based Design Can Help Your Next SoC

5 Reasons Why Platform Based Design Can Help Your Next SoC

Semiconductor design IP and verification IP have been around for decades, but just because your company has lots of IP doesn't mean that you're getting all of the benefits of a design reuse methodology.  Here are 5 reasons why platform based design can help your next SoC.

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Meeting Time-to-Market and Cost Reduction Goals Through Platform Based Design

Meeting Time-to-Market and Cost Reduction Goals Through Platform Based Design

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Companies designing today's complex System-on-Chips (SoC’s) must find new ways to meet the challenges imposed by shrinking time-to-market windows and cost pressures.  Platform based design methodologies allow companies to reduce the time it takes to bring designs to market and maximize reuse of internal IP on those designs.  A platform is the starting point for a new or derivative design that contains all of the IP and design meta data properly configured to be downloaded to a user's workspace.  To enable a platform based design methodology, companies must formalize how design IP is handled.  By adopting an IP Lifecycle Management solution (IPLM), companies can benefit from streamlining the SoC development process and guarantee that IP is being fully utilized through all of the company’s design projects.

WarpStor Case Study: Fabless SoC Design Company

WarpStor Case Study: Fabless SoC Design Company

In this customer environment, 200GB workspaces are common and can take up to 30 mins to fully populate. The general logistics around disk space management, delays in getting up current design data, and NFS latencies were a major source of delay for designers with a material impact on time-to-market. 

The team installed a WarpStor appliance including local storage on their network and project workspaces were built on the appliance.  User workspace creation time and disk space needs were reduced dramatically:

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  • Average workspace population time was reduced from 20-30mins to 14s
  • User workspace sizes decreased from 150GBto 100KB
  • Total IOPs down by more than 70% during write bursts

WarpStor Case Study: U.S. Based Flash Memory Company

WarpStor Case Study: U.S. Based Flash Memory Company

Multiple workspaces created for regression runs can overwhelm traditional lers when they write back regression results and log files.  

The team installed a WarpStor appliance in front of their SAN. All regression workspaces were built on the WarpStor appliance.  Filer write performance was improved dramatically:

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  • Up to 10x reduction in random writes due to buffering/coalescing on WarpStor Appliance
  • Up to 20% improvement in raw throughput of random writes
  • Utilization of the filer reduced by almost 50% during write bursts
  • Total IOPs down by more than 70% during write bursts

Go Native - With Methodics at DAC in Austin

Go Native - With Methodics at DAC in Austin

DAC 2016 in Austin will be another exciting event for Methodics.  We'll be featuring the second major release of our IP Lifecycle Management platform, ProjectIC, along with a new release of WarpStor, our partnerships with Perforce and Magillem, hula dancers, and much more!

Untitled Document
Methodics News

Welcome to Our DAC 2016 Newsletter!


Hi there, and welcome to the last newsletter before the main conference of the year, DAC!

This is going to be our best DAC ever! I know, I know, all vendors like to say that, but for us this year its really true.

First up, we have some incredible live Hawaiian dance performances at our booth (twice daily) to break up the demo/sales-pitch/swag-grab grind. This is part of our “Go Native” theme for integrating native data tools (such as Perforce) into our IP Management flow. Every other vendor in the data/IP management space is trying to sell you a proprietary “closed” system solution, ultimately with the goal of locking you in. Don’t do it! .. Go Native!

And by the way, we'll have several of our friends from Perforce joining us at our booth this year too.  Please be sure to stop by to meet with them and hear more about the advantages of adopting native Perforce.

Also we’ll be announcing the next release of our flagship product, the ProjectIC 2.0 IP Lifecycle Management (IPLM) solution with a focus on Platform Based Design. This new release is a major step forward for us and includes performance improvements, richer API’s, and some killer new features. Platform Based Design is a process that is getting increasing amounts of traction in today's IP-centric Semiconductor design environment.  How ProjectIC 2.0 can facilitate this is discussed in a new white paper here.

Finally, we’ll be announcing a new release of WarpStor with new features and integrations to help reduce your workspace creation/management and release bottlenecks. We’ll also be presenting some customer success stories to help explain how this technology has helped other companies in the Semiconductor space.

I hope to see all of you in Austin on June 6th!

Best Regards,
Simon

P.S. - If one or more of the topics covered in this newsletter grabs your interest, please email dac16@methodics.com and let us know if you'd like to hear more about it.

DAC 2016 Logo

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ProjectIC Logo



WarpStor Logo



VersIC Logo



Perforce Logo






Come see us at DAC 2016 in Austin

It's DAC time again, and Methodics once again has a lot happening!  Please visit us at booth #1019 at the Austin Convention Center, to learn about  exciting advances in our technology:

  • ProjectIC v2.0 - This second major release of our flagship IP Lifecycle Management (IPLM) solution enables platform-based design... an industry-first!

  • WarpStor - our engineering workspace, diskspace, and IO bandwidth optimizer is helping customers drastically reduce costs and improve time-to-market.  See the links below for customer success stories.

  • Integration with Magillem tools to provide a fully synchronized IPLM and SoC assembly environment, assuring that designs can be quickly assembled and kept up to date with changes in the underlying IP.

We are also excited to be involved in other activities around the show including a presentation at the Cadence Theater at 1:30pm on Wednesday, June 8 titled "IP Lifecycle Management - Enabling Platform Based Design"

To pre-schedule a private meeting at our booth or learn more, email dac16@methodics.com.

And, on a final note...  Please drop by our booth to pick up a special gift and qualify for our our daily fitbit give-away!


Magillem Logo


Hawaiian Lei

Fitbit One
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White Paper: Meeting Time-to-Market and Cost Reduction Goals Through Platform Based Design

   by: Michael Munsey, VP of Business Development and Strategic Accounts

Companies designing today's complex System-on-Chips (SoC’s) must find new ways to meet the challenges imposed by shrinking time-to-market windows and cost pressures.  Platform based design methodologies allow companies to reduce the time it takes to bring designs to market and maximize reuse of internal IP on those designs.

A platform is the starting point for a new or derivative design that contains all of the IP and design meta data properly configured to be downloaded to a user's workspace.  To enable a platform based design methodology, companies must formalize how design IP is handled.

By adopting an IP Lifecycle Management solution (IPLM), companies can benefit from streamlining the SoC development process and guarantee that IP is being fully utilized through all of the company’s design projects.

read more >>


Website Highlights

Whitepaper: Meeting Time-to-Market and Cost Reduction Goals Through Platform Based Design
Press Release: Methodics Expands Worldwide Sales Team to Meet Strategic Initiatives
Press Release:
Methodics and Magillem Team Up to Deliver an Industry First IP Assembly Platform Based Development Environment
Award Announcement: Methodics receives 2016 Perforce award for "Most Innovative Integration"
SemiWiki Blog: Bulking Up of Design Data Calls for Version Control on Steroids
WarpStor Case Study 1: A U.S. Based Flash Memory Company
WarpStor Case Study 2
: A Fabless SoC Design Company