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Webinar Recap: IP Lifecycle Management and Traceability

Webinar Recap: IP Lifecycle Management and Traceability

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by Daniel Payne, SemiWiki

Earlier this month, I attended a webinar organized by Methodics on the topic of IP life cycle management and traceability, with three presenters and a Q&A session at the end.

Semiconductor IP creation and re-use is the foundation of all modern IC designs, and keeping track of hundreds to thousands of IP blocks along with design scripts and verification results becomes a complicated process very quickly, especially if you’re still using a manual approach.

Read the full recap here >>

Cloud-Based Functional Verification

Cloud-Based Functional Verification

By Daniel Payne, SemiWiki

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The big three EDA vendors are constantly putting more of their tools in the cloud in order to speed up the design and verification process for chip designers, but how do engineering teams approach using the cloud for functional verification tests and regressions?

At the recent Cadence user group meeting (CDNLive) there was a presentation by Vishal Moondhra from Methodics, "Creating a Seamless Cloudburst Environment for Verification".

Click here to read the full article >>

Traceability and Design Verification Synergy

Traceability and Design Verification Synergy

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by Daniel Payne, SemiWiki

The IC design and verification process can be comprised of many independent point tools, or for more synergy you can have tools that work together by a more synergistic process. We've all heard the maxim, "Work smarter, not harder." A white paper just came out from Methodics on a smarter approach, Traceability for the Design Verification Process, so I've taken the time to read the 9 pages and then present my findings. 

Click here to read the full article >>

How Well Did Methodics do in 2018?

How Well Did Methodics do in 2018?

In January, I read from the ESDA Alliance about EDA and Semiconductor IP revenues increasing 6.7% for Q3 2018, reaching $2,435.6 million, which is decent growth for our maturing industry. In stark contrast there's a company called Methodics that specializes in Intellectual Property Lifecycle Management (IPLM) and traceability that has a much higher growth rate than the industry average. To get better informed, I spent some time asking questions of two contacts at Methodics: Jerry Brocklehurst, VP of Marketing and Simon Butler, President and CEO.

Read the full SemiWiki interview by Daniel Payne here>>

SoC Design Partitioning to Save Time and Avoid Mistakes

SoC Design Partitioning to Save Time and Avoid Mistakes

I started designing ICs in 1978 and continued through 1986, and each chip used hierarchy and partitioning but our methodology was totally ad-hoc, and documented on paper, so it was time consuming to make revisions to the chip or train someone else on the history or our chip, let alone re-use any portion of our chips again. Those old, manual ways of doing ...

>> Read More at SemiWiki

Using IP in a SoC Compliant with ISO 26262

Using IP in a SoC Compliant with ISO 26262

The automotive segment is being well served by semiconductor suppliers of all sizes because of the unit volumes, and the constant push to automate more of the driving decisions to silicon and software can raise lots of questions about safety, reliability and trust. Fortunately the ISO standards body has already put in place a functional safety compliance specification known as ISO 26262, so engineers working at automotive companies have a clear idea how to document their processes to ensure that you and I as consumers are going to be safe while driving the old fashioned way with our hands on the wheel, or more towards the goal of autonomous driving which will be hands-free. Semiconductor designers can use dozens to hundreds of IP blocks in their automotive chips, so one challenge is how to be compliant with iSO 26262 while managing so many blocks.

Read more of Daniel Payne’s SemiWiki blog here >>

IP Management Using both Git and Methodics

IP Management Using both Git and Methodics

I use Quicken to manage my business and personal finances because it saves me so much time by downloading all of my transactions from Chase for credit card, Amazon for credit card, Wells Fargo for banking and Schwab for IRA. Likewise, for IP management in SoC design you want an app like Quicken that plays well with other tools that you are already familiar with. Such is the case with IP management as many engineers have used Git before to manage their software source code projects they can also use Git to manage their RTL code because they are related text files.

The challenge comes in SoC design when you want to start managing IC design files that are binary like IC layout, AMS designs or even SPICE waveform files. Perforceis a popular version management system that can handle these binary files quite well, so how would you connect Perforce and Git together cohesively? 

CLICK HERE to read the SemiWiki article:

ISO 26262 Traceability Requirements for Automotive Electronics Design

ISO 26262 Traceability Requirements for Automotive Electronics Design

Reading the many articles on SemiWiki and other publications we find experts talking about the automotive market, mostly because it's in growth mode, has large volumes and vehicles consume more semiconductors every year. OK, that's on the plus side, but what about functional safety for automotive electronics? Every time that an autonomous car has an accident or a fatality it makes front page news on CNN and across social media, so we're keen to understand how safety is supposed to protect us from driving mishaps. The automotive industry has already published a functional safety standard known as ISO 26262, which is a necessary first step, and for us in the design community we need to be aware that this standard mandates traceability requirements. 

 CLICK HERE to read the SemiWiki article:

Combining IP and Product Lifecycle Tools

Combining IP and Product Lifecycle Tools

Systems design has been around for decades and has been enabled by the widespread use of Product Lifecycle Management (PLM) tools that help manage the process of starting with an idea then tracking details through the end of life.  Our own semiconductor industry caught hold of the PLM concepts first from the mechanical CAD companies looking for new markets, so they really focused on "part" management and some design process data.  

Today, as design nodes get smaller and smaller, the associated data sets are exploding and companies are adopting IP reuse strategies to remain profitable by leveraging their existing assets. This means big incentives to integrate a PLM tool at the system level along with a semiconductor IP Lifecycle Management (IPLM) tool, creating a coherent process across the entire product lifecycle.

CLICK HERE to read the SemiWiki article:(URL:  https://www.semiwiki.com/forum/content/7374-combining-ip-product-lifecycle-tools.html)

SoC Design Management with Git

SoC Design Management with Git

While Git is a very popular data management tool for software developers, there are many good reasons to pick a different solution for SoC design.  For starters, Git is designed to control text files, not binary files.  Also, there are recommended limits on the total repository size as well as file sizes.  So what is the recommended alternative?

 

CLICK HERE to read the SemiWiki article.(URL:  https://www.semiwiki.com/forum/content/7298-soc-design-management-git.html)

Hierarchy Applied to Semiconductor IP Reuse

Hierarchy Applied to Semiconductor IP Reuse

When I first started doing IC design back in 1978 we had hierarchical designs, and that was doing a relatively simple 16Kb DRAM chip with only 32,000 transistors using 6um (aka 6,000 nm) design rules. SoC designs today make massive use of hierarchy at all levels of IC design: IC Layout, transistor netlist, gate level netlist, RTL level, C or SystemC level, embedded software, software drivers, firmware. Our semiconductor IC business is based on both IP and EDA tools being able to handle hierarchy effectively.

CLICK HERE  to read the article

Improving Time-To-Market With The Right IPLM Solution

Improving Time-To-Market With The Right IPLM Solution

In the increasingly competitive semiconductor market, getting a product out on time is of critical importance. Missing market windows by even a few months can mean the difference between being highly profitable vs breaking even or even losing millions in revenue. In this scenario, it is of critical importance for teams to be able to reuse existing, proven IPs to reduce development time, complexity and cost. An IPLM (IP Lifecycle Management) solution like Methodics’ Percipient is designed to help customers adopt an IP-centric design flow to address this need. To fully capitalize on IP reuse, the IPLM system needs to be built from the ground up to handle the realities and complexities of identifying and reusing IP resources . This white paper discusses one of the key components of Percipient - the Graph Database - that helps the tool achieve its goal of enabling fast and seamless IP reuse

Rethinking IP Lifecycle Management

Rethinking IP Lifecycle Management

We recently saw both Apple and Samsung introduce new smart phones, and realize that the annual race to introduce sophisticated devices that are attractive and differentiated is highly competitive. If either of these companies misses a market window then fortunes can quickly change. SoCs with billions of transistors like smart phone processors make semiconductor IP re-use a central approach in design productivity, instead of starting from scratch for each new generation.

CLICK HERE  to read the article

NEW CONCEPTS IN SEMICONDUCTOR IP LIFECYCLE MANAGEMENT

NEW CONCEPTS IN SEMICONDUCTOR IP LIFECYCLE MANAGEMENT

Right before #54DAC I participated in a webinar with Methodics on "New Concepts in Semiconductor IP Lifecycle Management" with Simon Butler, CEO of Methodics, Michael Munsey, Vice President of Business Development and Strategic Accounts, and Vishal Moondhra, Vice President of Applications. The webinar introduced “percipient” and how it will not only extend IP Lifecycle Management, but allow for the modeling of the entire design ecosystem. Percipient was then featured in the Methodics booth at #54DAC with demos and presentations. 

CLICK HERE  to read the article.

THE SEMICONDUCTOR BRIDGE: A CONNECTED IPLM

THE SEMICONDUCTOR BRIDGE: A CONNECTED IPLM

Electronic Design Magazine, June 26, 2017


Development processes in large semiconductor organizations need to scale, and they can do so by adopting the same flexibility and agile principles as software companies.

CLICK HERE to read the article.

Webinar -New Concepts in Semiconductor IP Lifecycle Management

Webinar -New Concepts in Semiconductor IP Lifecycle Management

The semiconductor IP market continues growing at a healthy rate, and IP reuse is a staple of all modern SoC designs. Along with the acceptance of IP reuse comes a host of growing challenges, like:
 

  • Increase in design files
  • Increase in meta-data
  • More links between design members worldwide
  • More links between data in multiple engineering systems


Companies like Methodics have been serving the IP lifecycle management segment for many years now, however there comes a point where the increases in design complexity call for a new approach, so to find out what is coming next you are invited to a webinar where their next generation platform is being unveiled:

CLICK HERE  to read the article.

NEW CONCEPTS IN SEMICONDUCTOR IP LIFECYCLE MANAGEMENT

NEW CONCEPTS IN SEMICONDUCTOR IP LIFECYCLE MANAGEMENT

Excel is a wonderful, general purpose spreadsheet tool that lets me organize and analyze rows and columns of data into something meaningful, however it doesn't know anything about requirements traceability for complex semiconductor projects. So why do so many engineering teams still rely upon Excel or custom, in-house tools? It's probably because of perceived lower costs, institutional momentum, and the typical NIH (Not Invented Here) syndrome. Safety critical industries like automotive, aircraft and medical all have standards that must be adhered to during the design process, and they share a common need - requirements traceability from concept through production. Two software companies have teamed up to integrate their toolsets into something that really does help teams achieve requirements traceability, Jama Software and Methodics. I just attended their joint webinar and will share what they talked about.

CLICK HERE  to read the article.

CTO Interview: Peter Theunis of Methodics

CTO Interview: Peter Theunis of Methodics

CLICK TO DOWNLOAD

CLICK TO DOWNLOAD

Fascinated by computers at a very young age, Peter got his degree in Computer Science and was brought to the Bay Area via AIESEC Berkeley’s student exchange program to write his thesis. He has now more than 15 years of professional experience in software engineering, large scale systems architecture and data center engineering in Silicon Valley startups as well as with Yahoo! where he spent the last 9 years as a systems architect and principal engineer.

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SoC integration using IP Lifecycle Management Methodology

SoC integration using IP Lifecycle Management Methodology

Small EDA companies often focus on a single point tool and then gradually over time they add new, complementary tools to start creating more of a sub-flow to help you get that next SoC project out on time. The most astute EDA companies often choose to partner with other like-minded companies to create tools that work together well, so that your CAD department doesn't have to cobble together a working solution. I was pleased to find two such EDA companies that have worked well together on SoC integration using IP lifecycle management methodology, Methodics and Magillem

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IP Reuse Requires a Single-Source-of-Truth

IP Reuse Requires a Single-Source-of-Truth

As semiconductor companies adopt IP reuse strategies to improve engineering efficiencies and achieve time-to-market advantages, modern data management (DM) tools are built on industry standard version control systems that provide a "single-source-of-truth" architecture.  

In his latest article "IC Design Management: Build or Buy?" on SemiWiki, Daniel Payne discusses the benefits of this architecture in contrast to  commercial or homegrown systems built around an older style "server-per-project" architecture.

You can read the complete article here:  https://www.semiwiki.com/forum/content/6388-ic-design-management-build-buy.html