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Hierarchy Applied to Semiconductor IP Reuse

Hierarchy Applied to Semiconductor IP Reuse

When I first started doing IC design back in 1978 we had hierarchical designs, and that was doing a relatively simple 16Kb DRAM chip with only 32,000 transistors using 6um (aka 6,000 nm) design rules. SoC designs today make massive use of hierarchy at all levels of IC design: IC Layout, transistor netlist, gate level netlist, RTL level, C or SystemC level, embedded software, software drivers, firmware. Our semiconductor IC business is based on both IP and EDA tools being able to handle hierarchy effectively.

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Enabling Hierarchical IP Reuse using Private Resources

Enabling Hierarchical IP Reuse using Private Resources

Introduction

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As design complexity increases and design cycles shrink, IP reuse has become a critical component of success for hardware teams. However, these two realities are often at odds with each other - complex IPs are hard to create, test and reuse. On the other hand, SOCs need to be able to incorporate more and more complex IPs from diverse sources in as seamless and low effort manner as possible.

One way to manage complexity is break down IPs into simpler components and build the complex pieces up hierarchically. While this is good for managing complexity, it introduces a host of issues that need to be handled by the IP management system to allow for hierarchical reuse of IPs.

Percipient introduces the concept of Private Resources to help ease this burden and allow teams to make meaningful progress in IP reuse.

Improving Time-To-Market With The Right IPLM Solution

Improving Time-To-Market With The Right IPLM Solution

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In the increasingly competitive semiconductor market, getting a product out on time is of critical importance. Missing market windows by even a few months can mean the difference between being highly profitable vs breaking even or even losing millions in revenue. In this scenario, it is of critical importance for teams to be able to reuse existing, proven IPs to reduce development time, complexity and cost. An IPLM (IP Lifecycle Management) solution like Methodics’ Percipient is designed to help customers adopt an IP-centric design flow to address this need. To fully capitalize on IP reuse, the IPLM system needs to be built from the ground up to handle the realities and complexities of identifying and reusing IP resources . This white paper discusses one of the key components of Percipient - the Graph Database - that helps the tool achieve its goal of enabling fast and seamless IP reuse

Rethinking IP Lifecycle Management

Rethinking IP Lifecycle Management

We recently saw both Apple and Samsung introduce new smart phones, and realize that the annual race to introduce sophisticated devices that are attractive and differentiated is highly competitive. If either of these companies misses a market window then fortunes can quickly change. SoCs with billions of transistors like smart phone processors make semiconductor IP re-use a central approach in design productivity, instead of starting from scratch for each new generation.

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Improving Time-To-Market With The Right IPLM Solution

Improving Time-To-Market With The Right IPLM Solution

Introduction

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In the increasingly competitive semiconductor market, getting a product out on time is of critical importance. Missing market windows by even a few months can mean the difference between being highly profitable vs breaking even or even losing millions in revenue.

In this scenario, it is of critical importance for teams to be able to reuse existing, proven IPs to reduce development time, complexity and cost. An IPLM (IP Lifecycle Management) solution like Methodics’ Percipient is designed to help customers adopt an IP-centric design flow to address this need.

To fully capitalize on IP reuse, the IPLM system needs to be built from the ground up to handle the realities and complexities of identifying and reusing IP resources . This white paper discusses one of the key components of Percipient - the Graph Database - that helps the tool achieve its goal of enabling fast and seamless IP reuse.

Something New in IP Lifecycle Management

Something New in IP Lifecycle Management

Last month at DAC I met up with Michael Munsey of Methodics to get a quick update on what has been happening over the past 12 months within his company, and he quickly invited me to watch an archived webinar on their latest tool for IP Lifecycle Management called Percipient. I love to play the board game Scrabble, so i had to Google the word Percipient to learn its meaning, "having a good understanding of things, perspective". OK, that's my new word for the day then.

We often blog about new and updated point EDA tools on SemiWiki, so it's refreshing to learn more about the category of EDA tools that works throughout all of the tools and IP used on a SoC project. System-level complexity has become so large that the days of using Excel to track semiconductor IP usage or EDA tool usage fall woefully inadequate. 

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NEW CONCEPTS IN SEMICONDUCTOR IP LIFECYCLE MANAGEMENT

NEW CONCEPTS IN SEMICONDUCTOR IP LIFECYCLE MANAGEMENT

Right before #54DAC I participated in a webinar with Methodics on "New Concepts in Semiconductor IP Lifecycle Management" with Simon Butler, CEO of Methodics, Michael Munsey, Vice President of Business Development and Strategic Accounts, and Vishal Moondhra, Vice President of Applications. The webinar introduced “percipient” and how it will not only extend IP Lifecycle Management, but allow for the modeling of the entire design ecosystem. Percipient was then featured in the Methodics booth at #54DAC with demos and presentations. 

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THE SEMICONDUCTOR BRIDGE: A CONNECTED IPLM

THE SEMICONDUCTOR BRIDGE: A CONNECTED IPLM

Electronic Design Magazine, June 26, 2017


Development processes in large semiconductor organizations need to scale, and they can do so by adopting the same flexibility and agile principles as software companies.

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Webinar -New Concepts in Semiconductor IP Lifecycle Management

Webinar -New Concepts in Semiconductor IP Lifecycle Management

The semiconductor IP market continues growing at a healthy rate, and IP reuse is a staple of all modern SoC designs. Along with the acceptance of IP reuse comes a host of growing challenges, like:
 

  • Increase in design files
  • Increase in meta-data
  • More links between design members worldwide
  • More links between data in multiple engineering systems


Companies like Methodics have been serving the IP lifecycle management segment for many years now, however there comes a point where the increases in design complexity call for a new approach, so to find out what is coming next you are invited to a webinar where their next generation platform is being unveiled:

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NEW CONCEPTS IN SEMICONDUCTOR IP LIFECYCLE MANAGEMENT

NEW CONCEPTS IN SEMICONDUCTOR IP LIFECYCLE MANAGEMENT

Excel is a wonderful, general purpose spreadsheet tool that lets me organize and analyze rows and columns of data into something meaningful, however it doesn't know anything about requirements traceability for complex semiconductor projects. So why do so many engineering teams still rely upon Excel or custom, in-house tools? It's probably because of perceived lower costs, institutional momentum, and the typical NIH (Not Invented Here) syndrome. Safety critical industries like automotive, aircraft and medical all have standards that must be adhered to during the design process, and they share a common need - requirements traceability from concept through production. Two software companies have teamed up to integrate their toolsets into something that really does help teams achieve requirements traceability, Jama Software and Methodics. I just attended their joint webinar and will share what they talked about.

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CTO Interview: Peter Theunis of Methodics

CTO Interview: Peter Theunis of Methodics

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Fascinated by computers at a very young age, Peter got his degree in Computer Science and was brought to the Bay Area via AIESEC Berkeley’s student exchange program to write his thesis. He has now more than 15 years of professional experience in software engineering, large scale systems architecture and data center engineering in Silicon Valley startups as well as with Yahoo! where he spent the last 9 years as a systems architect and principal engineer.

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SoC integration using IP Lifecycle Management Methodology

SoC integration using IP Lifecycle Management Methodology

Small EDA companies often focus on a single point tool and then gradually over time they add new, complementary tools to start creating more of a sub-flow to help you get that next SoC project out on time. The most astute EDA companies often choose to partner with other like-minded companies to create tools that work together well, so that your CAD department doesn't have to cobble together a working solution. I was pleased to find two such EDA companies that have worked well together on SoC integration using IP lifecycle management methodology, Methodics and Magillem

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Fabless SOC Design Company - Creating Large Workspaces with WarpStor

Fabless SOC Design Company - Creating Large Workspaces with WarpStor

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In this customer environment 200GB workspaces are common and can take up to 30 mins to fully populate. The general logistics around disk space management, delays in getting up current design data and NFS latencies were a major source of delay for designers with a material impact on time-to-market. 

U.S. Based Flash Memory Company - Improving Filer Random Write Performance with WarpStor

U.S. Based Flash Memory Company - Improving Filer Random Write Performance with WarpStor

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Multiple workspaces created for regression runs can overwhelm traditional lers when they write back regression results and log les. This is particularly true when many short tests complete at roughly the same time. With WarpStor’s buffered write-through cache accumulating writes and bursting them to the ler, write performance can be dramatically increased. 

IP Reuse Requires a Single-Source-of-Truth

IP Reuse Requires a Single-Source-of-Truth

As semiconductor companies adopt IP reuse strategies to improve engineering efficiencies and achieve time-to-market advantages, modern data management (DM) tools are built on industry standard version control systems that provide a "single-source-of-truth" architecture.  

In his latest article "IC Design Management: Build or Buy?" on SemiWiki, Daniel Payne discusses the benefits of this architecture in contrast to  commercial or homegrown systems built around an older style "server-per-project" architecture.

You can read the complete article here:  https://www.semiwiki.com/forum/content/6388-ic-design-management-build-buy.html

Leveraging ‘Single Source of Truth’ Architecture to Speed Development Times, Improve Design Quality, and Reduce Risk

Leveraging ‘Single Source of Truth’ Architecture to Speed Development Times, Improve Design Quality, and Reduce Risk

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Many Design Management (DM) tools used by the Semiconductor Industry today are based on outdated, proprietary version control systems and have fallen significantly behind the state of the art. These tools are often only capable of supporting a single project per server due to the severe scalability and performance limitations inherent in their underlying technology. This ‘server per project’ limitation siloes teams and their information, preventing sharing and reuse across the organization.

This paper describes how modern DM tools are built on industry standard version control systems to take a centralized, IP based approach - one that leverages a ‘Single Source of Truth’ architecture for Platform Based Design and enables a high degree of design reuse to speed development times, improve quality, and reduce risk.

All Things IP: SemiWiki's Daniel Nenni interviews Methodics CEO, Simon Butler

All Things IP: SemiWiki's Daniel Nenni interviews Methodics CEO, Simon Butler

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"IP" and "IP Reuse" mean different things to different people.  For many years, Methodics has been helping semiconductor companies implement IP reuse strategies.  In this interview, Simon covers important trends in methodologies that help customers stay competitive in the face of ever-tightening margins.  

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Integrating Requirements Management with IP Management

Integrating Requirements Management with IP Management

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This paper describes how a requirements management system like Jama can be integrated into the IP management platform ProjectIC, allowing users to see IP requirements right in the context of their SoC.

Such integration represents one more step forward to reaching the important goal of implementing IP reuse strategies that reduce development costs, improve time-to-market, and keep semiconductor companies profitable in today’s highly competitive SOC marketplace. 

5 Reasons Why Platform Based Design Can Help Your Next SoC

5 Reasons Why Platform Based Design Can Help Your Next SoC

Semiconductor design IP and verification IP have been around for decades, but just because your company has lots of IP doesn't mean that you're getting all of the benefits of a design reuse methodology.  Here are 5 reasons why platform based design can help your next SoC.

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Meeting Time-to-Market and Cost Reduction Goals Through Platform Based Design

Meeting Time-to-Market and Cost Reduction Goals Through Platform Based Design

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Companies designing today's complex System-on-Chips (SoC’s) must find new ways to meet the challenges imposed by shrinking time-to-market windows and cost pressures.  Platform based design methodologies allow companies to reduce the time it takes to bring designs to market and maximize reuse of internal IP on those designs.  A platform is the starting point for a new or derivative design that contains all of the IP and design meta data properly configured to be downloaded to a user's workspace.  To enable a platform based design methodology, companies must formalize how design IP is handled.  By adopting an IP Lifecycle Management solution (IPLM), companies can benefit from streamlining the SoC development process and guarantee that IP is being fully utilized through all of the company’s design projects.