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Creating a Seamless Cloudburst Environment for Verification

Creating a Seamless Cloudburst Environment for Verification

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With every new generation and project, the effort required to close verification increases dramatically, requiring 1000’s of tests and regressions that put inordinate amounts of pressure on the internal infrastructure. This paper explores how to seamlessly shift some of this workload to the cloud - aka cloudburst – where jobs can run in an elastic infrastructure and can expand as needed.

To download the white paper, please click the PDF image.

IPLM as a Driver of Global Access Control

IPLM as a Driver of Global Access Control

An IP Lifecycle Management tool like Percipient is the core of IP based design workflows. It is the central repository of the design Bill Of Materials and serves as a hub of information for design and IP reuse related activities. This is done by providing an IP centric view of the entire design universe within an enterprise.

In most practical situations, permissions play a key role in the design process. Teams need to control the permissions of IPs for many reasons - proprietary technology, contractual obligations and simply to control the spread of particular IPs within the organization.

This white paper discusses the challenges of permissions management using various IP assets across multiple projects and across a worldwide organization.

To download the white paper, please click the PDF image to the right.

Traceability for the Design Verification Process

Traceability for the Design Verification Process

This white paper talks about adding traceability to design verification that allows teams to definitively and easily document the exact state of the verification at any point in the design process. This provable, documented status of verification is particularly important when trying to meet FuSa specifications like ISO26262 and DO- 254.

To download the white paper, please click the PDF image to the right.

ISO 26262 Compliance In An IP Based Development Flow

ISO 26262 Compliance In An IP Based Development Flow

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There are many advantages to managing your design development activity in an IP-centric methodology. Optimally partitioned designs, where each block is treated as a reusable, self-contained IP with versioned dependencies on other blocks allows teams to be significantly more lean, agile, and flexible.

In addition to making the design process itself more efficient, an IP-centric methodology also allows users to attach relevant metadata to each IP. This metadata - engineering details, bugs, requirements, and ISO26262 compliance information - is as integral to an IP as its design files and dependencies.

ISO26262 compliance can be demonstrated using a survey designed by a compliance expert or team, and filled out by the design expert. These surveys and their responses are then used to determine the compliance or fitness of a particular part (or IP in this case) for an application that needs to meet certain functional safety (FuSa) standards.

This paper details a process to simplify the FuSa process for an ISO 26262 compliant flow for semiconductors by showing how templates can be used to automate the survey and response components of the FuSa process.

Design Partitioning with Percipient

Design Partitioning with Percipient

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Semiconductor designs are most efficiently managed as related sets of functional blocks, and significant benefits can be achieved by fully aligning the overall development flow with this in mind.

Percipient enables users to abstract each functional block to a special data object, called an IP.  By abstracting to the IP level, powerful top down flows that simultaneously maintain a real-time connection to the lowest level design data are made possible.

This paper describes best practices for optimally partitioning designs using an IP management system that provides full traceability while removing any overhead burden from the end user.



Accelerating Innovation in Semiconductor Development (a Siemens-Methodics Perspective)

Accelerating Innovation in Semiconductor Development (a Siemens-Methodics Perspective)

PLM systems help businesses run their entire operation by creating an environment where all product data and metadata can be organized, accessed, and analyzed.  Historically, PLM systems came from mechanical CAD companies and were intended to combine part management and design process information, a relatively static environment.

In contrast, semiconductor design is a highly dynamic, iterative process that requires instantaneous access to quickly evolving data.  In order to meet time-to-market demands and confront the exponentially growing costs of semiconductor fabrication, companies have adopted intellectual property (IP) reuse to streamline semiconductor development.  By assembling designs made up of existing IP, they can reduce the time of development, and maximize the investment in the development of these IP blocks.


To enable this IP-reuse design methodology, companies must have an IP lifecycle management (IPLM) system that understands the highly dynamic nature of semiconductor development environment in addition to a more traditional PLM system.

By combining a best-in-class PLM system with a best-in-class IPLM system, a “digital thread” can be created that starts during product ideation and definition of requirements, and traces all the way through the semiconductor design process. It can then continue into manufacturing, and to sales and support, creating an environment where all the important information is interlinked and tracked.

In this way, requirements from the product ideation process can be linked to semiconductor IP, creating a traceable link that shows the specific product requirements that are met by that IP. During semiconductor verification, functional coverage results at the IP level can then be tracked and related back to the IP.  Companies that must achieve Functional Safety (FuSa) standards compliance, such as ISO26262 for the automotive Industry, can do so while, at the same time, reduce their costs by maximizing IP reuse and reduce time-to-market.


This white paper describes how a semiconductor company can benefit from using a best-in-class PLM solution integrated with a best-in-class IP management solution to achieve these goals.

An IP-Centric Approach to Git Based Development

An IP-Centric Approach to Git Based Development

About this Whitepaper
How to establish an IP-Centric methodology in a Git workflow.

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Content and Organization

Information provided in this document is organized in the following parts: • IP-Centric Design Methodology
• Working with a Git IP
• Restrictions on Git Repositories

Intended Audience

The business process owners supporting product management, design engineering, program management, product planning, product master data management, and release operations will all have a stake in the subjects discussed in this white paper. Information technology professionals can use this document as a roadmap for reducing system overhead costs, consolidating systems, eliminating integrations, and reducing system support requirements.

High-Availability Architecture for Enterprise IPLM

High-Availability Architecture for Enterprise IPLM

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About this Whitepaper

Addressing the need for 24/7 availability for infrastructure in an Enterprise IPLM environment.

Content and Organization

Information provided in this document is organized in the following parts: • The Need for High Availability in Enterprise IPLM Systems
• ArchitectingPercipientforHA

Intended Audience

The business process owners supporting product management, design engineering, program management, product planning, product master data management, and release operations will all have a stake in the subjects discussed in this white paper. Information technology professionals can use this document as a roadmap for reducing system overhead costs, consolidating systems, eliminating integrations, and reducing system support requirements.