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Improving Time-To-Market With The Right IPLM Solution

Improving Time-To-Market With The Right IPLM Solution

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In the increasingly competitive semiconductor market, getting a product out on time is of critical importance. Missing market windows by even a few months can mean the difference between being highly profitable vs breaking even or even losing millions in revenue. In this scenario, it is of critical importance for teams to be able to reuse existing, proven IPs to reduce development time, complexity and cost. An IPLM (IP Lifecycle Management) solution like Methodics’ Percipient is designed to help customers adopt an IP-centric design flow to address this need. To fully capitalize on IP reuse, the IPLM system needs to be built from the ground up to handle the realities and complexities of identifying and reusing IP resources . This white paper discusses one of the key components of Percipient - the Graph Database - that helps the tool achieve its goal of enabling fast and seamless IP reuse

Something New in IP Lifecycle Management

Something New in IP Lifecycle Management

Last month at DAC I met up with Michael Munsey of Methodics to get a quick update on what has been happening over the past 12 months within his company, and he quickly invited me to watch an archived webinar on their latest tool for IP Lifecycle Management called Percipient. I love to play the board game Scrabble, so i had to Google the word Percipient to learn its meaning, "having a good understanding of things, perspective". OK, that's my new word for the day then.

We often blog about new and updated point EDA tools on SemiWiki, so it's refreshing to learn more about the category of EDA tools that works throughout all of the tools and IP used on a SoC project. System-level complexity has become so large that the days of using Excel to track semiconductor IP usage or EDA tool usage fall woefully inadequate. 

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Meeting Time-to-Market and Cost Reduction Goals Through Platform Based Design

Meeting Time-to-Market and Cost Reduction Goals Through Platform Based Design

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Consumer demands will continue to pressure companies to deliver new and innovative products.  SoC design companies need to find ways to meet ever shrinking market windows while design complexity continues to grow.

Platform based design methodologies allow SoC design teams to deliver against these technology and market pressures by allowing for maximum design reuse and simplification of the new product design development environment.  The key to enabling this methodology is the ability to organize all the company's design assets into a base set of design platforms and to institute an IP Lifecycle Management system to support this methodology.  

 

 

An Innovative SoC Integration Workflow

An Innovative SoC Integration Workflow

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SoC Integration is a challenging and important task that all hardware teams undertake on a regular basis.

A SoC is typically made up of series of IPs, each of which could also be a sub-system in its own right. The key role of integration is to accept new releases of the component IPs and/or sub-systems, and verify whether these newer releases work in the context of the SoC.  The releases that are available for integration should have passed some quality control of their own - i.e. basic checks that ensure that the release that is available for integration satisfies a minimum quality level, and moves the SoC forward. 

This white paper describes an integration flow methodology, and how various roles involved in the process - integrator, contributor, and consumer - interact to assure successful integration of component IPs and sub-systems.

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Problems and Challenges of Using PLM in a Semiconductor Design Environment

Problems and Challenges of Using PLM in a Semiconductor Design Environment

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Product Lifecycle Management (PLM) was first introduced by automobile and defense companies in the mid 1980’s with the goal of reducing development cost and speeding up the product development process.

While PLM systems have seen success in these and other industries with large design teams and well established methodologies, the adoption rate in the semiconductor space has been slow. This can be attributed to a number of factors.

This white paper discusses the problems and challenges of trying to use a PLM system in the semiconductor design environment and presents an alternative solution that provides the most critical functions of a PLM system, but without the cost and increased maintenance overhead.

Best Practices for Perforce Based Hardware Design

Best Practices for Perforce Based Hardware Design

A typical chip design project consists of several designers with a diverse mix of disciplines, each working on a different aspect of the design with different flows, and generating large amounts of diverse data.  For example, there are RTL and verification teams, analog and mixed signal designers, layout engineers and silicon engineering teams.  In this environment, data management tools like Perforce Helix manage a substantial portion of the data.

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Our latest white paper, written in partnership with Perforce, that presents a list of the unique challenges associated with the many diverse sets of data generated during hardware design, and discusses the advantages of adopting a release-based flow versus a branch/merge flow.

Managing Your Design Environment as Hierarchical IPs

Managing Your Design Environment as Hierarchical IPs

An important part of any project is the set of tools chosen to perform design work, and their associated configuration files. Typically, the project lead or responsible CAD person will decide on these tools ahead of time, and many tradeoffs are considered when making these choices.  Then, once work begins, these choices are generally locked down for the duration of the project.  However, tools, PDKs, simulation libraries, and other design environment resources will each go through their own revisions during the lifecycle of a project.

Given this background, we can see that an IP-centric process around tool selection and design environment management can be used in the same way that functional blocks are managed in the design.  

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This paper presents and discusses a methodology for including design environment resources as hierarchical IP blocks within the design project itself, and how its versions and lifecycle changes can be managed alongside the other IP’s in the project.

Supporting the Concept of "IP@HEAD"

Supporting the Concept of "IP@HEAD"

During the early part of developing an IP, one or more users rapidly add new features, bug fixes etc to the IP. In this phase of IP development, having to ‘release’ an IP for these rapid changes to be visible to the rest of the team is cumbersome and unnecessary. To address this mode of work, ProjectIC supports the notion of IP@HEAD.

 

 

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Methodics Application Note IP@Head

Managing IP Views to Assure Timely, High Quality Releases

Managing IP Views to Assure Timely, High Quality Releases

In today's hardware design environments, IP’s are often thought of as self contained “black boxes” where the IP is instantiated in a design based on a specific release version. This lends itself well to hierarchical designs where a project can be assembled using these releases and a stable, well-understood configuration of the design can be sent for production.

In reality, these IP’s are each organized using subfolders (“Views”) containing different categories of files, each of which is developed on its own release schedule.  This creates a number of challenges when multi-disciplinary teams are working on different blocks and yet need to remain coordinated across the overall project to assure timely, high-quality releases.

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Our new white paper titled "IP Views" discusses the various challenges and the available solutions that lead to better convergence on working Silicon.

Keeping the Crown Jewels Secure

Keeping the Crown Jewels Secure

Securing IP design data is critical. It's rather like saying that it's a good idea to have security in the Tower of London to stop the crown jewels being stolen. IP blocks are the crown jewels of an SoC company.  Paul McLellan of SemiWiki describes the importance of securing design data in his latest blog titled "Threat Detection: How to Keep the Crown Jewels Secure."  You can read all about it here.

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You can also read our related white paper titled "Threat Detection through Big Data Analytics - A Proactive Approach to Securing SoC IP Design Data."

The Magnificent Seven of International IP Management

The Magnificent Seven of International IP Management

Almost all large projects these days are distributed across multiple geographic locations. As the world rotates underneath the sun, the focus of activity moves too: Europe, US, China, India, back to Europe. For this to work effectively requires a collaborative platform designed for multi-site design efforts, a platform that communicates the current state of the design, planned changes, history, and delivers what each site requires with minimal user intervention and maximum efficiency. 

When looking for an IP management platform, there are seven key elements that you will want architected in, not added on.  Paul McLellan covers these seven items in his SemiWiki article titled "The Magnificent Seven of International IP Management".

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Our associated white paper titled "Architected for Multi-Site Collaboration" can be download below.

 

Effective Bug Tracking with IP Sub-systems

Effective Bug Tracking with IP Sub-systems

We posted another Semiwiki article that should be of interest to our SoC customers this time on the topic IP-centric bug tracking. The old project-centric model for managing bugs is less relevant for IP based solutions and bugs must be aggregated from the entire resource hierarchy. This means that the traditional software-centric Jira/Teamforge/Bugzilla usemodels need to be re-thought.