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Putting the “I” in PLM

Putting the “I” in PLM

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The complexity of today’s semiconductor devices rivals the complexities of systems design in other industries, and the semiconductor industry can learn a lot from the evolution of systems design. One of the advancements of the past two decades has been the adoption of product lifecycle management (PLM) solutions to manage system designs from ideation through end of life.  PLM systems help businesses run their entire operation by creating an environment where all product data and metadata can be organized, accessed, and analyzed.  PLM systems allow information to be made available immediately and consumed in formats that make sense for each stakeholder.   However, once the data is in the PLM system, it is generally stabilized and static in nature.

In contrast, semiconductor design is a highly dynamic, iterative process that requires instantaneous access to quickly evolving data. This data needs to be rapidly assembled and integrated into highly specialized design and verification tools.  Traditional PLM systems are not designed to handle the "high velocity" nature of this changing data.

In order to get the best of both worlds, the ideal solution is for a best in class PLM solution to interface with a best in class semiconductor IP lifecycle management (IPLM) solution.  Semiconductor companies can then reap the benefits of both an optimized semiconductor IP-Centric and IP-Reuse design methodology in conjunction with streamlined and cost-efficient business processes.

Percipient: Taming Git for the Enterprise

Percipient: Taming Git for the Enterprise

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Git brings significant flow improvements to software and digital design, but these improvements come with heavy costs in increased complexity. This increased complexity is driven by the practical limits on Git repository sizes, leading to a proliferation of independent repositories, which in turn puts a greater burden on system integration and tracking.  The question is whether Git’s benefits justify the resultant increase in complexity and risk.  Percipient, the IP Lifecycle Management (IPLM) platform from Methodics, eliminates the trade-off; enterprises can leverage the power of Git and simplify their integration flow at the same time.

Samsung Advanced Computing Lab (ACL)

Samsung Advanced Computing Lab (ACL)

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The ACL design build environment requires 1,000’s of runs consuming 1,000’s of CPU hours and many Terabytes of data on a continuous basis. These numbers are expected to continue to increase as ACL grows. Having top of the tree clean workspace is key requirement for build infrastructure where workspaces are created and deleted very frequently and the average life of work spaces was less than a week.

Enabling Hierarchical IP Reuse using Private Resources

Enabling Hierarchical IP Reuse using Private Resources

Introduction

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As design complexity increases and design cycles shrink, IP reuse has become a critical component of success for hardware teams. However, these two realities are often at odds with each other - complex IPs are hard to create, test and reuse. On the other hand, SOCs need to be able to incorporate more and more complex IPs from diverse sources in as seamless and low effort manner as possible.

One way to manage complexity is break down IPs into simpler components and build the complex pieces up hierarchically. While this is good for managing complexity, it introduces a host of issues that need to be handled by the IP management system to allow for hierarchical reuse of IPs.

Percipient introduces the concept of Private Resources to help ease this burden and allow teams to make meaningful progress in IP reuse.

Improving Time-To-Market With The Right IPLM Solution

Improving Time-To-Market With The Right IPLM Solution

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In the increasingly competitive semiconductor market, getting a product out on time is of critical importance. Missing market windows by even a few months can mean the difference between being highly profitable vs breaking even or even losing millions in revenue. In this scenario, it is of critical importance for teams to be able to reuse existing, proven IPs to reduce development time, complexity and cost. An IPLM (IP Lifecycle Management) solution like Methodics’ Percipient is designed to help customers adopt an IP-centric design flow to address this need. To fully capitalize on IP reuse, the IPLM system needs to be built from the ground up to handle the realities and complexities of identifying and reusing IP resources . This white paper discusses one of the key components of Percipient - the Graph Database - that helps the tool achieve its goal of enabling fast and seamless IP reuse

Improving Time-To-Market With The Right IPLM Solution

Improving Time-To-Market With The Right IPLM Solution

Introduction

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In the increasingly competitive semiconductor market, getting a product out on time is of critical importance. Missing market windows by even a few months can mean the difference between being highly profitable vs breaking even or even losing millions in revenue.

In this scenario, it is of critical importance for teams to be able to reuse existing, proven IPs to reduce development time, complexity and cost. An IPLM (IP Lifecycle Management) solution like Methodics’ Percipient is designed to help customers adopt an IP-centric design flow to address this need.

To fully capitalize on IP reuse, the IPLM system needs to be built from the ground up to handle the realities and complexities of identifying and reusing IP resources . This white paper discusses one of the key components of Percipient - the Graph Database - that helps the tool achieve its goal of enabling fast and seamless IP reuse.

Something New in IP Lifecycle Management

Something New in IP Lifecycle Management

Last month at DAC I met up with Michael Munsey of Methodics to get a quick update on what has been happening over the past 12 months within his company, and he quickly invited me to watch an archived webinar on their latest tool for IP Lifecycle Management called Percipient. I love to play the board game Scrabble, so i had to Google the word Percipient to learn its meaning, "having a good understanding of things, perspective". OK, that's my new word for the day then.

We often blog about new and updated point EDA tools on SemiWiki, so it's refreshing to learn more about the category of EDA tools that works throughout all of the tools and IP used on a SoC project. System-level complexity has become so large that the days of using Excel to track semiconductor IP usage or EDA tool usage fall woefully inadequate. 

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WEBINAR VIDEO - NEW CONCEPTS IN SEMICONDUCTOR IP LIFECYCLE MANAGEMENT

WEBINAR VIDEO - NEW CONCEPTS IN SEMICONDUCTOR IP LIFECYCLE MANAGEMENT

New Concepts in Semiconductor IP Lifecycle Management

Today's complex SoC design requires a new level of internal and external design traceability and reuse by tightly coupling IP creators with IP consumers. Join us for the introduction of an exciting new platform that allows companies to provide the transparency and control needed to streamline collaboration by providing centralized cataloging, automated notifications to design teams, flexible permissions across projects, and integrated analytics across diverse engineering systems. Come see how companies are realizing substantial cost and time to market savings by adopting IP lifecycle management methodologies.

Integrating Requirements Management with IP Management

Integrating Requirements Management with IP Management

Introduction

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Increasing design and verification complexity in SoCs is leading many teams to adopt industry standard best-practices for managing their projects.

One of the key components to successfully managing a distributed, complex and time-critical SoC project is Requirements Management. Having a full set of requirements, easily managed and updated for the project makes it much easier to bring transparency and tracking to a project.

Once requirements management is in place, it is also essential to be able to tie requirements back to the context of the IPs being used in the SoC. Since IP management and requirements management are two separate systems, being able to connect these two is critical. This paper describes how a requirements management system like Jama can be integrated into the IP management platform ProjectIC, allowing users to see IP requirements right in the context of their SoC.

Fabless SOC Design Company - Creating Large Workspaces with WarpStor

Fabless SOC Design Company - Creating Large Workspaces with WarpStor

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In this customer environment 200GB workspaces are common and can take up to 30 mins to fully populate. The general logistics around disk space management, delays in getting up current design data and NFS latencies were a major source of delay for designers with a material impact on time-to-market. 

U.S. Based Flash Memory Company - Improving Filer Random Write Performance with WarpStor

U.S. Based Flash Memory Company - Improving Filer Random Write Performance with WarpStor

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Multiple workspaces created for regression runs can overwhelm traditional lers when they write back regression results and log les. This is particularly true when many short tests complete at roughly the same time. With WarpStor’s buffered write-through cache accumulating writes and bursting them to the ler, write performance can be dramatically increased. 

Methodics / Magillem Integration for SOC Designers

Methodics / Magillem Integration for SOC Designers

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The ProjectIC / Magillem interface provides SoC designers, IP creators, IP consumers, and IP integrators the ability to take advantage of both ProjectIC and Magillem tools from within a unified workspace.

Leveraging ‘Single Source of Truth’ Architecture to Speed Development Times, Improve Design Quality, and Reduce Risk

Leveraging ‘Single Source of Truth’ Architecture to Speed Development Times, Improve Design Quality, and Reduce Risk

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Many Design Management (DM) tools used by the Semiconductor Industry today are based on outdated, proprietary version control systems and have fallen significantly behind the state of the art. These tools are often only capable of supporting a single project per server due to the severe scalability and performance limitations inherent in their underlying technology. This ‘server per project’ limitation siloes teams and their information, preventing sharing and reuse across the organization.

This paper describes how modern DM tools are built on industry standard version control systems to take a centralized, IP based approach - one that leverages a ‘Single Source of Truth’ architecture for Platform Based Design and enables a high degree of design reuse to speed development times, improve quality, and reduce risk.

Integrating Requirements Management with IP Management

Integrating Requirements Management with IP Management

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This paper describes how a requirements management system like Jama can be integrated into the IP management platform ProjectIC, allowing users to see IP requirements right in the context of their SoC.

Such integration represents one more step forward to reaching the important goal of implementing IP reuse strategies that reduce development costs, improve time-to-market, and keep semiconductor companies profitable in today’s highly competitive SOC marketplace. 

Meeting Time-to-Market and Cost Reduction Goals Through Platform Based Design

Meeting Time-to-Market and Cost Reduction Goals Through Platform Based Design

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Companies designing today's complex System-on-Chips (SoC’s) must find new ways to meet the challenges imposed by shrinking time-to-market windows and cost pressures.  Platform based design methodologies allow companies to reduce the time it takes to bring designs to market and maximize reuse of internal IP on those designs.  A platform is the starting point for a new or derivative design that contains all of the IP and design meta data properly configured to be downloaded to a user's workspace.  To enable a platform based design methodology, companies must formalize how design IP is handled.  By adopting an IP Lifecycle Management solution (IPLM), companies can benefit from streamlining the SoC development process and guarantee that IP is being fully utilized through all of the company’s design projects.

WarpStor Case Study: Fabless SoC Design Company

WarpStor Case Study: Fabless SoC Design Company

In this customer environment, 200GB workspaces are common and can take up to 30 mins to fully populate. The general logistics around disk space management, delays in getting up current design data, and NFS latencies were a major source of delay for designers with a material impact on time-to-market. 

The team installed a WarpStor appliance including local storage on their network and project workspaces were built on the appliance.  User workspace creation time and disk space needs were reduced dramatically:

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  • Average workspace population time was reduced from 20-30mins to 14s
  • User workspace sizes decreased from 150GBto 100KB
  • Total IOPs down by more than 70% during write bursts

WarpStor Case Study: U.S. Based Flash Memory Company

WarpStor Case Study: U.S. Based Flash Memory Company

Multiple workspaces created for regression runs can overwhelm traditional lers when they write back regression results and log files.  

The team installed a WarpStor appliance in front of their SAN. All regression workspaces were built on the WarpStor appliance.  Filer write performance was improved dramatically:

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  • Up to 10x reduction in random writes due to buffering/coalescing on WarpStor Appliance
  • Up to 20% improvement in raw throughput of random writes
  • Utilization of the filer reduced by almost 50% during write bursts
  • Total IOPs down by more than 70% during write bursts

Meeting Time-to-Market and Cost Reduction Goals Through Platform Based Design

Meeting Time-to-Market and Cost Reduction Goals Through Platform Based Design

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Consumer demands will continue to pressure companies to deliver new and innovative products.  SoC design companies need to find ways to meet ever shrinking market windows while design complexity continues to grow.

Platform based design methodologies allow SoC design teams to deliver against these technology and market pressures by allowing for maximum design reuse and simplification of the new product design development environment.  The key to enabling this methodology is the ability to organize all the company's design assets into a base set of design platforms and to institute an IP Lifecycle Management system to support this methodology.  

 

 

An Innovative SoC Integration Workflow

An Innovative SoC Integration Workflow

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SoC Integration is a challenging and important task that all hardware teams undertake on a regular basis.

A SoC is typically made up of series of IPs, each of which could also be a sub-system in its own right. The key role of integration is to accept new releases of the component IPs and/or sub-systems, and verify whether these newer releases work in the context of the SoC.  The releases that are available for integration should have passed some quality control of their own - i.e. basic checks that ensure that the release that is available for integration satisfies a minimum quality level, and moves the SoC forward. 

This white paper describes an integration flow methodology, and how various roles involved in the process - integrator, contributor, and consumer - interact to assure successful integration of component IPs and sub-systems.

projectic_based_soc_int_flow.jpg