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When I first started doing IC design back in 1978 we had hierarchical designs, and that was doing a relatively simple 16Kb DRAM chip with only 32,000 transistors using 6um (aka 6,000 nm) design rules. SoC designs today make massive use of hierarchy at all levels of IC design: IC Layout, transistor netlist, gate level netlist, RTL level, C or SystemC level, embedded software, software drivers, firmware. Our semiconductor IC business is based on both IP and EDA tools being able to handle hierarchy effectively.

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